1. Field of the Invention
The present invention relates to a semiconductor memory device and a memory controller that controls the same, and more particularly relates to a semiconductor memory device capable of entering in a power-down mode and a memory controller that controls the same. The present invention also relates to an information processing system including the semiconductor memory device and the memory controller.
2. Description of Related Art
For a semiconductor memory device represented by DRAM (Dynamic Random Access Memory), there is often prepared a power-down mode to reduce the current consumption of the device during a non-access time. For example, for a DDR3 (Double Data Rate 3) DRAM, a mode called a precharge power-down mode is prepared. The precharge power-down mode is a mode in which operations of several internal circuits are suspended in a state that all banks are precharged, and thus the current consumption during a non-access time is reduced.
The precharge power-down mode includes a fast exit mode and a slow exit mode (see JEDEC STANDARD, DDR3 SDRAM Specification, JESD79-3B (Revision of JESD79-3A, September 2007), April 2008, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION <URL:http://www.jedec.org/download/search/JESD79-3B.pdf>).
The fast exit mode is a mode in which an operation of a DLL (Delay Locked Loop) circuit is continuously activated even when the circuit is in the precharge power-down mode. When the fast exit mode is selected, although there is some current consumption by the DLL circuit, it is possible to return (exit) from the precharge power-down mode immediately. Therefore, the fast exit mode is preferable when frequently entering and returning of the circuit in and from the precharge power-down mode are repeated. Further, even in the precharge power-down mode, an ODT (On Die Termination) operation can be used in a synchronization mode, and thus it is possible to access to other Ranks with which a data input/output terminal is shared, in a usual manner and at a high speed.
On the other hand, the slow exit mode is a mode in which an operation of a DLL circuit is suspended when the circuit is in the precharge power-down mode. When the slow exit mode is selected, due to suspension of the DLL circuit, it is possible to minimize its current consumption. However, because the DLL circuit is suspended, the time required to return from the precharge power-down mode is longer, and at the same time, the ODT operation becomes non-synchronous in the precharge power-down mode. These factors reduce the speed for accessing other Ranks with which a data input/output terminal is shared.
As described above, the fast exit mode and the slow exit mode have their advantages and disadvantages. Whether to use either the fast exit mode or the slow exit mode is determined depending on a set value of a mode register. Conventionally, selection of these modes is made by using a mode-register set operation performed after inputting power.
Whether to use either the fast exit mode or the slow exit mode is determined depending on a set value of a mode register. Therefore, it is not practical to switch the modes as needed during a practical use. That is, to change the set value of the mode register, it is necessary to execute a mode register set (MRS) command, and after the MRS command is executed, it is not possible to input another command unless a predetermined time (tMOD) is elapsed. Therefore, there is a problem that when switching of the modes is frequently performed, an overhead becomes large.
Due to these circumstances, either one of the fast exit mode and the slow exit mode is selected after inputting power according to its system characteristics, and accordingly it has been rare to change the selected mode at the practical use. Therefore, there is another problem that, when the fast exit mode is selected, the fast exit mode is always used thereafter, and accordingly the current consumption becomes large, whereas when the slow exit mode is selected, the slow exit mode is always used thereafter, and accordingly the performance of the system is degraded.